//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012-2015 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor: Xilinx
// \   \   \/    Version: 1.2
//  \   \        Filename: top5x2_7to1_sdr_rx.v
//  /   /        Date Last Modified:  21JAN2015
// /___/   /\    Date Created: 2SEP2011
// \   \  /  \
//  \___\/\___\
// 
//Device:     7-Series
//Purpose:      SDR top level receiver example - 2 channels of 5-bits each
//
//Reference:    XAPP585.pdf
//    
//Revision History:
//    Rev 1.0 - First created (nicks)
//    Rev 1.1 - BUFG added to IDELAY reference clock
//    Rev 1.2 - Updated format (brandond)
//
//////////////////////////////////////////////////////////////////////////////
//
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//
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//////////////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module lvds4x2_1to7_sdr #
(
    parameter integer       D = 4,                              // Parameter to set the number of data lines
    parameter integer       N = 2,                              // Parameter to set the number of channels
//    parameter integer       MMCM_MODE = 1,                      // Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
    parameter real          CLKIN_PERIOD = 6.000,               // clock period (ns) of input clock on clkin_p
    parameter real          REF_FREQ = 200.0,                   // Reference clock frequency for idelay control, 200 or 300 Mhz
    parameter               HIGH_PERFORMANCE_MODE = "FALSE",    // Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
    parameter               DIFF_TERM = "FALSE",                // Parameter to enable internal differential termination
    parameter               USE_PLL = "FALSE",                  // Parameter to enable PLL use rather than MMCM use, note, PLL does not support BUFIO and BUFR
    parameter               SAMPL_CLOCK = "BUF_G",              // Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
    parameter               PIXEL_CLOCK = "BUF_G",              // Parameter to set pixel clock buffer type, BUF_R, BUF_H, BUF_G
    parameter               DATA_FORMAT = "PER_CLOCK"           // PER_CLOCK or PER_LINE data formatting
)
(
    input           rst_n,                    // reset (active low)
    input           refclkin,                // Reference clock for input delay control

    input           clkin1_p,  clkin1_n,            // lvds channel 1 clock input
    input   [3:0]   datain1_p, datain1_n,            // lvds channel 1 data inputs
    input           clkin2_p,  clkin2_n,            // lvds channel 2 clock input
    input   [3:0]   datain2_p, datain2_n,            // lvds channel 2 data inputs
    
    output          px_clk,                 // Pixel clock output
    output          VS0,
    output          VS1,
    output          HS0,
    output          HS1,
    output          DE0,
    output          DE1,
    output  [23:0]  dout0,
    output  [23:0]  dout1
);

wire            reset;
assign          reset = ~rst_n;

reg    [27:0]    old_rx1    ;        
reg    [27:0]    old_rx2    ;        
wire        refclkint ;         
wire        rx_mmcm_lckdps ;        
wire    [1:0]    rx_mmcm_lckdpsbs ;    
wire        rxclk_div ;
wire    [1:0]    clkin_p ;            
wire    [1:0]    clkin_n ;            
wire    [7:0]    datain_p ;        
wire    [7:0]    datain_n ;
wire    [55:0]    rxdall ;            
wire        delay_ready ;        
wire        rx_mmcm_lckd ;        

// 200 or 300 Mhz Generator Clock Input
IBUF iob_200m_in(
    .I                (refclkin),
    .O                 (refclkint));

BUFG bufg_200_ref (
    .I             (refclkint), 
    .O             (refclkintbufg)) ;

IDELAYCTRL icontrol (                          // Instantiate input delay control block
    .REFCLK            (refclkintbufg),
    .RST            (reset),
    .RDY            (delay_ready));


// Input clock and data for 2 channels
assign clkin_p  = {clkin2_p, clkin1_p} ;
assign clkin_n  = {clkin2_n, clkin1_n} ;
assign datain_p = {datain2_p, datain1_p} ;
assign datain_n = {datain2_n, datain1_n} ;
    
n_x_serdes_1_to_7_mmcm_idelay_sdr #(
    .D                  (D),                    // Number of data lines
    .N                  (N),                    // Number of channels
    .SAMPL_CLOCK        (SAMPL_CLOCK),
    .PIXEL_CLOCK        (PIXEL_CLOCK),
    .USE_PLL            (USE_PLL),
    .HIGH_PERFORMANCE_MODE     (HIGH_PERFORMANCE_MODE),
    .CLKIN_PERIOD       (CLKIN_PERIOD),         // Set input clock period
//    .MMCM_MODE        (MMCM_MODE),                // Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
    .DIFF_TERM          (DIFF_TERM),
    .DATA_FORMAT         (DATA_FORMAT))             // PER_CLOCK or PER_CHANL data formatting
rx0 (                          
    .clkin_p           (clkin_p),
    .clkin_n           (clkin_n),
    .datain_p             (datain_p),
    .datain_n             (datain_n),
    .enable_phase_detector    (1'b1),
    .rxclk            (),
    .idelay_rdy        (delay_ready),
    .rxclk_div        (rxclk_div),
    .reset             (reset),
    .rx_mmcm_lckd        (rx_mmcm_lckd),
    .rx_mmcm_lckdps        (rx_mmcm_lckdps),
    .rx_mmcm_lckdpsbs    (rx_mmcm_lckdpsbs),
    .clk_data          (),
    .rx_data        (rxdall),
    .bit_rate_value        (16'h0560),            // required bit rate value
    .bit_time_value        (),
    .status            (),
    .debug            ());

lvds4x2_mapping #(
    .DATA_FORMAT    (DATA_FORMAT)
)
lvds4x2_mapping_inst(
    .din        (rxdall),
    .VS0        (VS0),
    .VS1        (VS1),
    .HS0        (HS0),
    .HS1        (HS1),
    .DE0        (DE0),
    .DE1        (DE1),
    .dout0      (dout0),
    .dout1      (dout1)
);

assign px_clk = ~rxclk_div;
          
endmodule
